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Keywords: ASIC Timing Engineer, Location: Santa Clara, CA

Page: 2

Senior Firmware Engineer - Embedded SW/Microcontroller/Bare-Metal Drivers

consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly..., and packaging suppliers. What You Can Expect We are seeking an experienced Firmware Engineer to join our team with a primary...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 07 Feb 2026
Salary: $111070 - 166400 per year

Digital Physical Design Engineer

verification,static timing analysis,physical design engineering,asic design,high speed design About Company: UST is a global...Job Description: Digital Physical Design Engineer Technical Lead I - VLSI Who We Are: Born digital, UST...

Company: UST
Location: Santa Clara, CA
Posted Date: 07 Feb 2026
Salary: $87000 - 131000 per year

Memory Controller Design Engineer

Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The... engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 04 Feb 2026
Salary: $107400 - 161200 per year

Senior Post Silicon Feature Development Engineer

Hardware Engineer to join our Silicon Solutions Group. In this role, you will lead system-design efforts to improve... bring-up plans. Lead system design partnering with architecture, software, chip/board designers, ASIC, and operations team...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 29 Jan 2026

Senior Digital Design Engineer

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group. In this role... micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 23 Jan 2026

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP... expert, able to traverse from Synthesis to final design closure (timing and layout) involving latest EDA technologies...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Senior Signal and Power Integrity Engineer - Hardware

We are now looking for a Senior Signal & Power Integrity Engineer! NVIDIA has continuously reinvented itself over two... to optimize package, PCB, ASIC, mixed signal circuit What we need to see: BS/MS-Electrical Engineering or equivalent...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Nov 2025

Senior Principal Digital IC Design Engineer

Design Engineer at Marvell, you will be part of the DCE – Connectivity Business Group, contributing to the development... experience in developing, implementing, and testing high-performance communications ASIC products. Extensive experience in RTL...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 12 Nov 2025

Applied Machine Learning Engineer - VLSI Design

process variation analysis, VLSI circuit design and timing etc. Responsible for translating the requirements into a data...) 5+ years experience in circuit design, VLSI, ASIC, EDA, Silicon analysis is required Prior experience in Applied Math...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 08 Feb 2026

IP Logic Design Engineer

, area, and timing goals Delivers microarchitecture specifications (MAS) document along with detailed clear block diagram..., signal level description, clocking details, power and timing requirements to capture the implementation details and ensure...

Company: Intel
Location: Santa Clara, CA
Posted Date: 04 Feb 2026

AI ML Engineer, RTL Power Optimization – New College Grad 2026

, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis..., and how RTL decisions impact post‑layout power and timing. Familiarity with RTL implementation of low‑power techniques (e.g...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Jan 2026
Salary: $116000 - 189750 per year

Applied Machine Learning Engineer, Circuit Design - New College Grad 2026

and timing etc. Responsible for translating the requirements into a data science problem, architect and build solutions... in Electrical/Computer Engineering (or equivalent experience). Experience with VLSI, Circuit Design, CMOS Device Physics, Timing...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 24 Jan 2026
Salary: $116000 - 189750 per year

Design Engineer - Sensors

with test vectors ASIC synthesis, static timing analysis and other post-RTL tools needed for delivering timing-closed designs... devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 18 Jan 2026

Senior Principal Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 13 Dec 2025

Senior Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data... performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $89360 - 133900 per year

Senior Staff Engineer, Physical Design

and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data.../support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 06 Dec 2025
Salary: $124420 - 186400 per year

Senior SRAM Circuit Design Engineer

and optimize design for power, timing, area and yield You'll make the layout floorplan and work with layout designers to optimize... We will have creative new ideas to support existing tools and flows Develop and Perform timing characterization and circuit verification...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 20 Nov 2025