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Keywords: ASIC RTL Engineer, Location: Hyderabad, Telangana

Page: 1

ASIC RTL Engineer

, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem...RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet...

Company: Talent Worx
Posted Date: 02 Oct 2025

Sr Staff Engineer- RTL Design

Job Description Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC... development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design...

Posted Date: 19 Sep 2025

Lead Design Engineer - RTL Design

-outs. Experience in Designing RTL block for an SOC. Experience in integrating ASIC IP into an SOC. Experience with Arm..._ MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Silicon Design team at AMD you will help create leading edge...

Posted Date: 09 Jul 2025

Associate Staff Physical Design Engineer

team that drives end-to-end SoC implementation, from RTL to tape-out. We work closely with design, verification... Lead Engineer – Physical Design to join our Silicon Engineering team in Hyderabad. In this role, you will drive the design...

Company: Silicon Labs
Posted Date: 03 Oct 2025

Principal Engineer, Physical Design

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS...

Company: Qualcomm
Posted Date: 27 Sep 2025

Physical Design Engineer, Senior Staff

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical... environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS...

Company: Qualcomm
Posted Date: 27 Sep 2025

Lead DFT Engineer

beyond DFT into embedded processor firmware, complex chip simulation, RTL implementation for ASIC & FPGA and deep silicon debug..._ Lead DFT Engineer THE ROLE: Lead DFT engineer will lead strong engineering team on Scan, MBIST, iJTAG test development...

Posted Date: 21 Sep 2025

SOC Verification Engineer

level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM..._ SOC Verification Engineer THE ROLE: The focus of this role is to plan, build, and execute the verification of new...

Posted Date: 16 Sep 2025

SoC Verification Engineer

: · Proficient in IP/Sub-System/SOC level ASIC verification · Proficient in debugging firmware and RTL code using simulation tools..._ SoC Verification ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new...

Posted Date: 10 Sep 2025

Physical Design Engineer, Staff

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent...

Company: Qualcomm
Posted Date: 10 Aug 2025

Physical Design Engineer, Lead

Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical...+ year of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent...

Company: Qualcomm
Posted Date: 10 Aug 2025

Physical Design Engineer, Senior

with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement... In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC...

Company: Qualcomm
Posted Date: 20 Sep 2025

Physical Design Engineer, Sr Lead

environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS..., Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods...

Company: Qualcomm
Posted Date: 18 Sep 2025

Staff Verification Engineer

Responsibilities: Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog... simulation in both RTL and gate-level netlist, isolating issues in both module and system level. Scripting experience in Python...

Company: Semtech
Posted Date: 11 Sep 2025

Staff Verification Engineer

Responsibilities: Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog... simulation in both RTL and gate-level netlist, isolating issues in both module and system level. Scripting experience in Python...

Company: Semtech
Posted Date: 10 Sep 2025