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Keywords: ASIC/RTL Design Engineer, Location: Santa Clara, CA

Page: 3

Physical Design Methodology Engineer

, you will work closely with the architecture, IP design, RTL design, CAD, silicon technology teams and product engineers to achieve... collaterals PREFERRED EXPERIENCE: Experience in ASIC Physical Design and/or CAD development Hands-on experience with Place...

Posted Date: 09 Nov 2025

Senior Principal Digital IC Design Engineer

in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general-purpose microprocessors. RTL design experience..., above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Our design team works on state...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

Senior Power Analysis and Optimization Engineer, AI-LLM Systems

alone. Partner closely with Architects, Performance, Software, ASIC Design, and Physical Design teams to interpret power data, root... of energy consumption, power estimation, data movement, and low‑power design. Familiarity with Verilog and ASIC design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 25 Jan 2026

SOC IP Methodology Engineer - Custom SOC

Nvidia is hiring a Senior SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP... customer IP. You will also work with external ASIC companies if we decide to outsource some part of Nvidia design...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 22 Jan 2026

Senior Memory Controller Verification Engineer

experience. 3+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork...NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem...

Company: Nvidia
Location: Santa Clara, CA
Posted Date: 21 Jan 2026

Integration Engineer

engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design... design and RTL development (SystemVerilog, Verilog). Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence...

Company: Apple
Location: Santa Clara, CA
Posted Date: 07 Nov 2025
Salary: $126800 - 190900 per year

CPU DFT Verification Engineer

. Description As a CPU DFT Verification Engineer, you will have the following responsibilities: • Work closely with architecture, RTL... verification team focusing on DFT verification. In this highly visible role, you will be at the center of a chip design effort...

Company: Apple
Location: Santa Clara, CA
Posted Date: 29 Oct 2025

Sensor Engineer

tools. Experience with ASIC ECO flow, RTL sanity tools specific to Design Rule Checking and Clock Domain Crossing checks... devices. Job activities span the ASIC design process from specification definition, high-level design, coding and verification...

Company: Qualcomm
Location: Santa Clara, CA
Posted Date: 17 Jan 2026

Principal CAD Engineer

Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools.... You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design...

Company: Marvell
Location: Santa Clara, CA
Posted Date: 09 Jan 2026
Salary: $146850 - 220000 per year

Power Methodology Engineer, Data Center Hardware IPs

applications. Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL..., and reduction at various levels (architecture, RTL, circuit design) AI/ML Concepts: Familiarity with machine learning algorithms...

Posted Date: 27 Nov 2025